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ASIC Verification

We have extensive experience in ASIC & FPGA design verification for CPU's, graphics chips, and networking chips. We have done everything from writing test plans to directed and random tests to designing and implementing testbenches. Our software background allows us to implement C reference models very quickly. We also have an in-depth understanding of several different DV methodologies and coverage metrics. As a result, upper management should have a much clearer picture of the current quality of the design, therefore, enabling them to make a better decision of when to tape out.


  • C/C++
  • Perl
  • Tcl/Tk
  • Verilog
  • PLI
  • Specman E
  • CynLib
  • System C
  • Vera
  • Test Builder
  • Assembly
  • Promela

Devices Tested:

  • CPUs
  • Math co-processors
  • Graphics
  • Networking/Communications


  • Directed
  • Constrained Randomized
  • Fully Randomized
  • Golden Model
  • Generator/Database/Catcher/Comparator


  • Signal Scan
  • Verplex


  • Verilog & C co-simulation engine
  • C Golden Reference Model Simulators (Architectural, Cycle-Accurate)
  • Verilog Testbenches
  • Experimenting/Setting Overall Methodology
  • Perl Testbench Drivers
  • Perl Test Generators


  • Architectural C Models
  • ALU Test Generators
  • Packet Generators/Catchers
  • Perl Support Scripts


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